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Bio

ZSOLT TOKEI, IMEC
DISTINGUISHED MEMBER OF TECHNICAL STAFF

Zsolt Tokei joined imec in 1999 and since then held various technical positions in the organization. First as process engineer and researcher in the field of copper low-k interconnects then headed the metal section. Later he became principal scientist, program director nano-interconnects and in 2016, appointed as Distinguished Member of Technical Staff Interconnect. He earned M.S. (1994) in physics from the University Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian University Kossuth and the French University Aix Marseille-III, he obtained his PhD (1997) in physics and materials science. From 1998 he worked at the Max-Planck Institute of Düsseldorf, Germany, as a post-doctorate researcher. From the date of joining imec he continued working on a range of interconnect issues including scaling, metallization, electrical characterization, module integration, reliability and system aspects. He has authored or co-authored over 300 publications in international scientific journals and in international scientific proceedings. He has been or is currently committee member of several international conferences including, but not limited to IITC (International Interconnect Technology Conference), IEDM CRY (International Electron Device Conference, Characterization and Reliability), IRPS (International Reliability Physics Symposium), IPFA (International symposium on the Physical and  Failure Analysis of Integrated Circuits). He is frequent invited speaker or short course teacher at several international conferences on interconnect related topics.

 

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Presentation abstract

HOW TO SOLVE THE BEOL RC DILEMMA?

Interconnects play an important role both in logic and memory devices. Reducing BEOL RC has been an ongoing concern for many years. While methodologies exist for wiring FinFETs, the emergence of potential new device architectures forces us to rethink the interconnects above. The complexity lies in the need of simultaneous optimization of novel metallization schemes, materials, circuit, system and cost parameters. In order to enable more functions per given footprint, besides the classical dimensional scaling, innovations at the architecture, device, design and material level are necessary. Performance indicators such as power, speed, noise, bandwidth density and reliability need to be considered. There is a clear opportunity for interconnects to take part of enabling new and interesting options.

 

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