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SLIDER DIEDERIK VERKEST    
   

 

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Bio

DIEDERIK VERKEST, IMEC
PROGRAM DIRECTOR

Diederik VERKEST holds a Ph.D. in Applied Sciences from the KU Leuven (Belgium). After working in the VLSI design methodology group of IMEC  (Leuven, Belgium) in the domain of system-on-chip design, he joined IMEC’s process technology unit as director of imec's INSITE program focusing on co-optimization of design and process technology for sub-10nm nodes.

 

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Presentation abstract

MOVING LOGIC TO THE 3RD DIMENSION

By 2020, Moore’s Law scaling will see an unprecedented pressure. It is already a fact that since the 20nm node, the happy scaling era where dimensional scaling was the fuel to generate cheaper, faster and more power efficient technology nodes ran out of steam. Today, technologists use all possible  “scaling boosters” to keep the prophecy alive. These techniques trade design requirements with specific technology capabilities in a so-called design-technology co-optimization. However, soon the “third dimension” will be inevitable to keep density scaling. However, although the migration from 2D to 3D structures worked well in memory technologies, there are number of obstacles that will need to be overcome when applied to logic technologies. In this talk we will explore key enablers from technology up to circuits and systems for the extension of Moore’s Law to the 3rd dimension.

 

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